The flash type A/D converter simultaneously compares an analog input signal with a plurality of ascending reference potentials to determine the closest match between the two. For example, a 7 -bit A/D converter with the overflow bit uses 128 (i.e., 2.sup.7) comparators for performing the simultaneous comparisons. In A/D converters of the type exemplified by the IC, CA3300, from RCA, each comparator is alternately coupled to a respective one of the aforesaid plurality of reference potentials and the analog input signal through a coupling capacitor. The output of all the comparators connected to the reference potentials having a value less than the input signal exhibit one output state and the remaining comparators exhibit an opposite output state.
The outputs of the comparators are fed to logic circuitry (e.g., PLA), which produces a parallel, 7-bit binary code related to the magnitude of the analog input signal.
During each cycle, various capacitors (e.g., coupling capacitors and the gate and parasitic capacitances of the switching transistors) are discharged and recharged between the respective reference potentials and the input signal. When the input signal is at either extreme of the range of the reference potential levels, maximum current drain is produced on the reference potential ladder and the input signal source. On the other hand, when the input signal is at the midpoint of the reference potential levels, the current drain on the reference ladder and the input signal source is minimized since the various capacitors tend to be charged equally in the opposite directions during each cycle.
It is desirable to reduce the current drain on the reference ladder and the input signal source, since it introduces nonlinearities, and further reduces either the cycle rate of the A/D converter or decreases the accuracy of the converter for a fixed cycle rate.
U.S. Pat. No. 4,507,649, issued to Dingwall, et al., discloses one approach to the above-mentioned problem of heavy current drain. In the Dingwall et al. approach a field effect transistor (i.e., FET) is connected in series between each of the plurality of coupling capacitors and the input signal bus. The gate electrodes of the FET's are biased at D.C. potentials which are tailored to the relative position of the respective FET's along the reference ladder. The FET's are constrained to operate in the source follower mode with the various capacitors as the respective load elements for certain ranges of the input signal, so that the individual coupling capacitors cannot charge or discharge to a potential exceeding the respective FET's D.C. gate potential minus its threshold potential, and thereby reducing the loading on the reference ladder.
This invention discloses yet another concept for reducing the current drain on the reference ladder. In accordance with the present invention, the input signal is continuously made available to an intermediate group of comparators (e.g., middle 50%). In addition, the input signal is tested to determine if it is above or below the midpoint of the reference potential levels. If the input signal is above the midpoint, the lower group of comparators (e.g., lower 25%) receive a fixed lower voltage (e.g., 0.25 V.sub.REF), instead of the input signal, in order to preclude the various capacitors (i.e., coupling, gate and parasitic) in the lower group of comparators from fully charging to the relatively high input signal level during each cycle. On the other hand, if the input signal is below the midpoint, the upper group of comparators (e.g., upper 25%) are provided with a fixed higher voltage (e.g., 0.75 V.sub.REF), in lieu of the input signal, thereby preventing the various capacitors associated with the upper group of comparators from fully discharging to the relatively low input signal level during each cycle.